With the integrated circuit (IC) fabrication technology developing to a stage where the device feature sizes reach deep-submicron dimensions, all circuit MOS devices are employed as lightly-doped drain (LDD) structures, and the silicide process has been widely used in the diffusion layers of such MOS devices. Meanwhile, in order to reduce the series resistance due to diffusion in gate polysilicon, synthesis of polycrystalline compounds is also employed. These fabrication process improvements can result in significant increases in IC operation speed and integration, along with the MOS device gate oxide layer being increasingly thinned due to the scaling down of the IC component. However, the improvements also lead to a significant disadvantage. Deep submicron ICs are more vulnerable to electrostatic discharge (ESD) strikes which can cause failure of the circuits, leading to lower reliability of products in which such ICs are used.
ESD is an event that transfers an amount of charge from one object (e.g., the human body) to another (e.g., a chip). The existing anti-ESD requirements with respect to ICs all mainly concern the protection of static electricity from human body, and the human-body model (HBM) has been established which is the earliest and one of the most commonly-used ESD models.
HBM simulates a discharge from an electrostatically charged person to an IC chip pin when the person touches the pin with the hand. Therefore, an ESD event often occurs within the IC's input and output units, and internal supply-to-ground paths as well. This event may cause a very large current flowing through the IC chip in a very short period of time. In fact, ESD events account for 35% or higher of the causes of chip failure.
ESD protection circuit is designed to prevent a working circuit from acting as an ESD path and thus being damaged by guaranteeing that, for any pin of the circuit, there is an appropriate low-impedance bypass for guiding the current caused by an ESD event occurring at the pin to the power line, which is then discharged through an ESD current path established by another pin.
Referring to FIG. 1, which is a schematic circuit diagram of a first ESD clamp of the prior art, including an RC trigger circuit formed of a resistor RI and a capacitor C1, a plurality of inverters 10 constituted by pMOS and nMOS transistors, and a discharge transistor 20. The discharge transistor 20 is realized as an nMOS transistor. As an ESD pulse is typically a high-voltage, high-frequency signal, the discharge transistor 20 is required to be a bulky device with a large footprint, which is conflictive with the high integration trend in this industry. In addition, the bulky discharge transistor 20 tends to be associated with a significant leakage current Ioff which may affect the proper operation of the circuit.
Referring to FIG. 2, which is a schematic circuit diagram of a second ESD clamp of the prior art. The ESD clamp depicted in FIG. 2 is a silicon-controlled rectifier (SCR) in which N+ and P+ regions are formed in an Nwell substrate, and P+ and N+ regions in a Pwell substrate. Additionally, two transistors T1 and T2 are also formed in the substrates. In this case, ESD protection triggering requires breakdown of the p-n junctions, which leads to low efficiency and low sensitivity. In addition, there is a possibility of latch-up occurring in the SCR, which poses an additional risk.